1. Field of the Invention
The present invention generally relates to a frame transmitting and receiving method and a communication device using the same. More particularly, the present invention is concerned with a frame transmitting and receiving method and a communication device using the same, such as a transceiver, in a digital multiplexed communication system.
Nowadays, a digital multiplexed communication system is applied to not only a network in which data is transferred at an extremely high speed, but also a relatively-low-speed communication with terminal equipment. A variety of digital multiplexed communication systems has been proposed and used in practice.
For example, a TDM/TDMA (Time Division Multiplexing/Time Division Multiple Access) communication system is known as a two-way communication system necessary to realize interactive services in a CATV (CAble TeleVision) network or the like. In practice, various frame formats have been proposed in such a two-way communication system. Hence, it is desired to provide a frame transmitting and receiving method and apparatus suitably provided in an LSI formation. It may be required that such a method and apparatus is flexible with various frame formats and enables reductions in terms of development, power consumption and cost as well as down-sizing.
2. Description of the Related Art
Generally, the digital multiplexed communication system has a concept of a "frame" which is a periodical repetition and "time slot" which is a time-based definition. Hence, the assembling and disassembling of frames is carried out.
FIG. 1 is a diagram of frame formats, and FIG. 2 is a diagram for explaining time slots. In these figures, a down frame is a frame to be sent from a switch office to a terminal, and an up frame is a frame to be sent from a terminal to a switch office. The down frames are consecutively sent with a period of 4 ms, while the up frames are burst signals so that a guard time GT is provided. In other words, the down frame is time division multiplexing (TDM), while the up frame is the time division multiple access (TDMA) in which the burst signal is sent in response to an instruction from the switch station (sent to via the down frame).
Each of the up and down frames has a speech-communication channel (hereinafter, simply referred to as B channel), and a control channel. The control channel includes a maintenance channel (hereinafter, simply referred to as M channel), and two call control channels (C, D). One of the two call control channels is a D channel for telephone services, and the other channel is a C channel for video-on-demand (VOD) services.
The up frame includes channels AD and AC used to return acknowledge signals to the down control channels D and C, respectively. The channels have respective formats as shown in FIG. 1.
The down and up frames are summarized as follows.
Down Frame
frame directed to subscriber terminal to switch station PA1 F00-F31: single frame (125 .mu.s), time slots TS000-TS127; multiframe pattern is transmitted at time slots TS000 and TS001 of F00 PA1 C0-C3: C channels disassembled into single frames F01-F04 and sent; assigned time slots TS002-TS031 PA1 D0, D1: D channels disassembled into single frames F05 and F06 and sent; assigned time slots TS002-TS031 PA1 frame directed to switch station from subscriber terminal PA1 B00-B94: speech communication channel PA1 (a) performing a receive synchronizing process in which the frame is pulled in a given phase of a machine cycle equal to m which is equal to (1/N).times.L where L denotes the number of bits forming the frame, N is a positive integer and m is a positive integer larger than 2; PA1 (b) performing, in a receive process executing phase forming part of the same machine cycle as that of the step (a), a receive process in which receive control channel data contained in a received frame is written into a shared memory in accordance with first m-bit stream program information which defines the receive process and is stored in the shared memory; and PA1 (c) performing, in a transmit process executing phase forming another part of the same machine cycle, a transmit process in accordance with second m-bit stream program information which defines a transmit procedure and is stored in the shared memory while reading transmit control channel data stored in the shared memory, whereby the transmit control channel data is transmitted in a phase of a bit level or a clock level. PA1 (d) correcting a delay time of control channel data received under a situation in which there is a time difference between a detection of the pattern information carried out in the receive synchronizing process and a write timing of the shared memory; and PA1 (e) correcting a delay time of data to be transmitted under a situation in which there is a time difference between a read timing of the shared memory and a given transmit frame starting timing externally supplied. PA1 (d) generating a hunting timing of detecting a machine cycle level of a next frame by using the pattern information of the machine cycle level in the receive synchronizing process; and PA1 (e) converting the hunting timing of the next frame generated at the step (d) into timing information of the bit level for detecting pattern information contained in the next frame. PA1 (d) writing, when the second m-bit stream program information (operation code) relates to a speech-communication channel, the second m-bit stream program information and a header of the received frame stored in the shared memory into a speech-communication channel transmit memory (BTx-RAM 110) in the receive process executing phase and writing transmit speech-communication channel data externally supplied into the speech-communication channel transmit memory (from PCM codec 300, for example); and PA1 (e) reading, in the transmit process executing phase, the header and the transmit speech-communication channel data from the speech-communication channel transmit memory and transmitting the header and the transmit speech-communication channel data. PA1 (d) writing in the transmit process executing phase, when the first m-bit stream program information relates to a speech-communication channel, the first m-bit stream program information stored in the shared memory into a speech-communication channel receive memory (BRx-RAM 210), reading receive speech-communication channel data from the speech-communication channel receive memory in the transmit process executing phase, and externally outputting the receive speech-communication channel data; and PA1 (e) writing, in the receive process executing phase, the receive speech-communication channel data into the speech-communication channel receive memory according to the first m-bit stream program information. PA1 a machine clock generating circuit generating a machine clock having a machine cycle equal to a length of m bits where m is larger than 2 and equal to (1/N).times.L where L denotes the number of bits forming the frame and N is a positive integer; PA1 a receive synchronizing circuit which pulls the frame in a given phase of the machine cycle; PA1 a shared memory in which first and second m-bit stream program information respectively define a receive procedure and a transmit procedure, and transmit control channel data are stored beforehand; PA1 a transmit/receive process part which performs, in a receive process executing phase forming part of a same machine cycle as that processed by the receive synchronizing circuit, a receive process in which receive control channel data contained in a received frame into the shared memory in accordance with the first m-bit stream program information, and which performs, in a transmit process executing phase forming another part of the same machine cycle, a transmit process in accordance with the second m-bit stream program information while reading the transmit control channel data stored in the shared memory; and PA1 a transmit phase control circuit which transmits the transmit control channel data in a phase of a bit level or a clock level. PA1 a pattern information detecting circuit which detects the pattern information in the phase of the bit level; PA1 a receive frame synchronization protecting circuit which stabilizes a pattern information detecting operation of the pattern information detecting circuit; PA1 a received frame length counter which performs a count operation in the phase of the machine cycle; PA1 a pattern information synchronizing circuit which synchronizes a pattern information detecting signal output by the pattern information detecting circuit with the phase of the machine cycle level whereby another pattern information detecting signal synchronized with the machine cycle; and PA1 a phase level converting circuit which converts a pattern information hunting signal having the phase of the machine cycle level into another pattern information hunting signal having the phase of the bit level, and PA1 wherein: PA1 the received frame length counter starts the count operation in response to the pattern information detection signal having the phase of the machine cycle level, and generates the pattern information hunting signal having the phase of the machine cycle level immediately before one frame is counted by the received frame length counter; and PA1 the received frame synchronization protecting circuit protects the received frame synchronization by the another pattern information detection signal having the phase of the bit level from the pattern information detecting circuit and the pattern information hunting signal having the phase of the bit level. PA1 the transmit phase control circuit includes a transmit delay control circuit which controls a phase of a transmitted frame with respect to the phase of the received frame; and PA1 the received frame length counter activates the transmit delay control circuit by the received frame length counter so that the transmit delay control circuit is activated in advance of the phase of the received frame by a maximum delay control time. Hence, data can be transmitted at a desired transmit phase. PA1 the transmit delay control circuit comprises a delay counter having the phase of the machine cycle level, a first selector having the phase of the bit level and a second selector having the phase of the clock level; and PA1 bit-level and clock-level delay controls are sequentially carried out after a machine-cycle-level delay control is completed, so that the transmit/receive process part starts to access the shared memory. Hence, the transmit process part can operate at the machine cycle level, and the transmitted frame can be subjected to a very fine transmit delay control of the clock level. PA1 the transmit/receive process part includes a transmit result writing circuit which performs a write operation on a transmit data area of the shared memory; PA1 a specific bit of transmitted data corresponding to a guard time is made to relate to a transmit request flag; and PA1 when transmitted data read from the shared memory is the transmit request flag, the transmitted data is transmitted after the guard time and logically changing the specific bit to an original value in order to release the transmit request flag. Hence, the CPU can be notified of the completion of the transmit process by reading the state of the transmit request flag. PA1 a pattern information detecting circuit which detects the pattern information in the phase of the bit level; PA1 a receive frame synchronization protecting circuit which stabilizes a pattern information detecting operation of the pattern information detecting circuit; PA1 a received frame length counter which performs a count operation in the phase of the machine cycle; PA1 a pattern information synchronizing circuit which synchronizes a pattern information detecting signal output by the pattern information detecting circuit with a phase of the count operation of the received frame length counter; PA1 a receive-part periodic initialization executing circuit which initializes a receive part of the transmit/receive process part in accordance with the periodic initialization program information; and PA1 a phase-level converting circuit which converts a pattern information hunting signal of the phase of the machine cycle level generated at an end of the periodic initialization for the receive part into another pattern information hunting signal having a phase of the bit level, and PA1 wherein: PA1 the received frame length counter starts the initial setting and count operation in response to the pattern information detection signal having the phase of the machine cycle level; PA1 when the received frame length counter overflows, the received frame length counter activates the receive-part periodic initialization executing circuit, which generates the pattern information hunting signal of the phase of the machine cycle level after completion of the initialization at a given counter value X and activates the received frame length counter again; and PA1 the received frame synchronization protection circuit protects the received frame synchronization by the pattern information detection signal having the phase of the bit level from the pattern information detecting circuit and the pattern information hunting signal having the phase of the bit level from the phase level converting circuit. PA1 a transmit-part periodic initialization executing circuit which initializes a transmit part of the transmit/receive process part in accordance with periodic initialization program information; and PA1 a transmit delay control circuit which controls a transmit phase of a frame corresponding to the phase of the received frame, and PA1 wherein: PA1 the received frame length counter activates the transmit-part periodic initialization executing circuit in advance of the phase of the received frame by a timing Y equal to the sum of a maximum control time of the transmit delay control circuit and a time Z necessary to execute the transmit-part periodic initialization; and PA1 the transmit-part periodic initialization executing circuit activates the transmit delay control circuit when the time Z elapses after completion of the transmit-part periodic initialization. PA1 the transmit delay control circuit includes a delay counter of the machine cycle level, a first selector having the phase of the bit level, and a second selector having the phase of the clock level; PA1 the delay counter of the machine cycle level performs a delay control of the machine cycle level after activated; PA1 the first and second selectors sequentially perform delay controls of the bit level and clock level, and then a transmit process part of the transmit/receive process part starts the transmission process. PA1 the transmit/receive process part includes a transmit result writing circuit which performs a write operation on a transmit data area of the shared memory; PA1 a specific bit of transmitted data corresponding to a guard time is made to relate to a transmit request flag; and PA1 when transmitted data read from the shared memory is the transmit request flag, the transmitted data is transmitted after the guard time and logically changing the specific bit to an original value in order to release the transmit request flag. PA1 the CPU includes a common bus switching circuit for accessing the shared memory via the common bus; and PA1 the common bus switching circuit switches, when the receive process is completed according to the first m-bit stream program information, the common bus to the CPU and switches back to an original state immediately before the transmit process for each frame is started. PA1 the periodic initialization program information includes program information concerning an initialization of the transmit part and an initialization of the receive part; PA1 the initialization of the transmit part includes at least data indicative of an amount of delay in the transmit delay control; and PA1 the initialization of the receive part includes at least the pattern information. PA1 wherein: PA1 when the second m-bit stream program information relates to a speech-communication channel, the second m-bit stream program information and a header of the received frame stored in the shared memory (RAM) are written into a speech-communication channel transmit memory (BTx-RAM) in the receive process executing phase, and transmit speech-communication channel data externally supplied is written into the speech-communication channel transmit memory; and PA1 the header and the transmit speech-communication channel data are read, in the transmit process executing phase, from the speech-communication channel transmit memory and the header and the transmit speech-communication channel data are transmitted. PA1 wherein: PA1 when the first m-bit stream program information relates to a speech-communication channel, the first m-bit stream program information stored in the shared memory (RAM) is written, in the transmit process executing phase, into a speech-communication channel receive memory (BRx-RAM), and receive speech-communication channel data is read from the speech-communication channel receive memory in the transmit process executing phase, and is externally output; and PA1 the receive speech-communication channel data is written, in the receive process executing phase, into the speech-communication channel receive memory according to the first m-bit stream program information. PA1 the transmit phase control circuit includes a transmit frame length counter which performs a count operation in the phase of the machine cycle level, and a transmit mode setting circuit; PA1 the transmit mode setting circuit sets a slave mode at a given timing after a synchronization of the received frame is established, and a master mode in which a frame can be transmitted irrespective of presence/non-presence of the received frame; PA1 the received frame length counter activates the transmit delay control circuit in the slave mode; and PA1 the transmit frame length counter activates the transmit delay control circuit in the master mode. PA1 the receive synchronizing circuit includes a received input signal switching circuit and a receive mode setting circuit which can set a normal mode or a loop-back mode; and PA1 the received input switching circuit receives the transmitted frame when the receive mode setting circuit sets the loop-back mode.
M: maintenance channel (assigned time slots TS002-TS009) PA2 B: speech communication channel B00-B94 (for each single frame); assigned time slots TS032-TS126 PA2 -: unused time slots (TS000-TS031 of F07-F31) (TS127 of F00-F31) PA2 M: maintenance channel (2GT+31PW+1UW+2TID+4DT+2BCC)=42 bytes PA2 C: C channel (2GT+15PW+1UW+2TID+60DT+2BCC)=82 bytes PA2 D: D channel (2GT+15PW+1UW+2TID+28DT+2BCC)=50 bytes PA2 AC: acknowledge (ACK) channel for C channel (2GT+3PW+1UW+2TID+1DT+2BCC)=11 bytes PA2 AD: ACK channel for D channel (2GT+3PW+1UW+2TID+1DT+2BCC)=11 bytes PA2 (2GT+3PW+1UW+32PCM)=38 bytes PA2 2GT+3PW+1UW: header
Up frame
FIG. 3 is a block diagram of related art which performs transmission and reception processes while disassembling and assembling the above-mentioned frames. The structure shown in FIG. 3 is applied to a subscriber in-house device (which is also referred to as subscriber terminal) in a digital multiplexed communication having a CATV station in a CATV system.
A bit stream of a received frame from a decoder part of a modem (not shown) is applied to a receive process unit 101, which makes the received bit stream synchronized with a secondary clock signal different from a (primary) received clock signal with which the bit stream is synchronized. Hence, a jitter can be eliminated from the bit stream. The secondary clock signal is generated by a secondary clock generating unit 102, which includes a PLL (Phase-Locked Loop) circuit.
The receive process unit 101 detects a multiframing pattern from the bit stream synchronized with the secondary clock signal, and outputs it to a receive control unit 103. The unit 103 performs a known synchronization protection. When the synchronization is established, the receive control unit 103 notifies an external control CPU that the synchronization has been established.
When the receive control unit 103 receives a request for receiving data after the synchronization is established, the receive control unit 103 outputs start/stop timing signals to the receive process unit 101 and a B-channel receive process unit 104 in order to perform necessary processes for the control channels in conformity with the down frame format shown in FIG. 1. For example, a descrambling process and a CRC check process are carried out. The above timing signals can be generated by counting bits after the timing at which the multiframing pattern for synchronization is detected. When a given bit position is indicated by the count value, a corresponding necessary process is carried out. The receive process unit 101 inputs data while performing the necessary processes for the respective control channels, and writes the input data into a receive data buffer (not shown).
The B-channel receive process unit 104 receives PCM data positioned in a time slot specified by the timing signal from the receive control unit 103, and converts the PCM data into data which conforms with a PCM.CODEC interface.
A transmit control unit 105 is notified by the receive control unit 103 that the multiframing pattern is detected. When a request for transmitting data is received from the CPU, the transmit control unit 105 performs a transmit delay control so that a frame to be transmitted is started with a given phase difference with respect to the received frame, Further, the transmit control unit 105 performs a process base on the format of each of the burst signals.
The transmit control of the transmit control unit 105 is carried out by outputting start/stop signals to a transmit process unit 106 and a B-channel transmit process unit 107 in order to perform necessary processes for the control channels in conformity with the up frame format. For example, a scramble process and an addition of a block check character (BCC) are carried out. The above timing signals can be generated by counting bits based on the transmit frame starting timing. When a given bit position is indicated by the count value, a corresponding necessary process is carried out.
It should be noted that, in such a digital multiplexed communication like the CATV system there is a certain distance between the switch station and the subscriber terminal and there is a need to improve the transmission efficiency, the transmit delay control should be carried out at a precision equal to 1/n (n is less than 10) of the clock cycle. In such a case, the clock-based timing control is carried out.
Upon receipt of the transmit control signal, the transmit process unit 106 serially reads transmit data from a transmit data buffer (not shown), and assembles the transmit data into a burst. The burst signal thus formed is sent from the transmit process unit 106.
The B-channel transmit process unit 107 assembles PCM data received via the PCM.CODEC interface into the B-channel format. The assembled PCM data is output to the time slot specified by the timing signal from the transmit control unit 105.
A data transfer with the CPU is carried out so that data of the receive control channels is transferred via a receive bus line, and data of the transmit control channels is transferred via a transmit bus line. The access control of the transmit and receive buffers is carried out while the CPU refers to indications of the transmit and receive states.
The above-mentioned prior art has the following disadvantages. The various timing signals of the bit level or the clock level are generated based on the frame structure and are distributed to the bit processing function parts. Hence, the prior art does not flexibly correspond to a modification of the frame structure. Thus, it is very difficult to proceed with a detailed design of the transmit and receive devices or transceiver until the specification of the frame structure is defined in detail. As a result, it is impossible to efficiently develop the transmit and receive devices or transceiver.
In the case where the transmit frame is different from the receive frame, it is required to prepare a pseudo remote device in order to perform the transmission or the reception. This is troublesome.